(1) Field of the Invention
The present invention relates to a false path detection program, and more particularly, to a false path detection program used for the timing analysis and verification of a digital circuit.
(2) Description of the Related Art
When designing semiconductor devices such as LSI circuits, CAD (Computer Aided Design) is used. Semiconductor circuits designed by CAD often include false paths that are not used in their functions.
CAD has the function of false path detection and timing analysis. With this function, where the maximum delay time from the input to the output of a certain circuit involves a delay time attributable to a false path, for example, the maximum delay time can be shortened so that the circuit can operate in a time shorter than the maximum delay time.
The following three methods are known as conventional methods for false path detection and timing analysis: The first method is to determine whether each of paths from the input to the output of a circuit is a false path or not (see, e.g., Unexamined Japanese Patent Publication No. H08-180098 (paragraph nos. [0014]-[0031]; FIGS. 2-11), and H.-C. Chen and D. H.-C. Du, Path sensitization in critical path problem, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 12(2): 196-207, February 1993). There has also been proposed a method of using higher-level operation description information in determining whether each path is a false path or not (see, e.g., Unexamined Japanese Patent Publication No. 2002-342403 (paragraph nos. [0019]-[0032]; FIGS. 1-3)). The second method is to obtain the shortest possible delay time while decreasing the value of delay time by degrees from a certain upper limit value (see, e.g., S. Devadas, K. Keutzer, and S. Malik, Computation of floating mode delay in combinational circuits: Theory and algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 12(12): 1913-1923, December 1993). In this method, the shortest possible delay time is obtained while ignoring a delay time attributable to a false path. The third method is a method (called dynamic timing analysis) in which delay times of input vectors (several input signals) are calculated by simulation (see, e.g., D. Brand and V. S. Iyengar, Timing analysis using functional analysis, IEEE Transactions on Computer, 37(10): 1309-1314, October 1988). There has also been proposed a method based on the third method and improved in efficiency (see, e.g., Unexamined Japanese Patent Publication No. 2001-67383 (paragraph nos. [0053]-[0069]; FIG. 1)). As seen from these publications, circuit design using CAD requires false path analysis.
However, in cases where the conventional false path analysis techniques are applied to large-scale, complex circuit design, considerable time is required for the analysis. In the first method in which the analysis is performed path by path, in extreme cases the number of paths exponentially increases with scale of circuit, requiring much time for the false path analysis. In the second method in which the value of delay time is decreased by degrees from a certain upper limit value, the number of times the false path analysis needs to be performed increases if the set range in which the delay time is decreased is narrow. In the third method in which input vectors are simulated, for n inputs, the false path analysis needs to be performed 2n times, requiring impractically long computation time.
In the timing analysis, only false paths with critical timing or timing error may be detected to reduce the processing time needed for the false path analysis. In recent years, however, circuits with higher performance are demanded, and when such circuits are designed, there exist innumerable false paths with critical timing or timing error, making the detection of such false paths impractical.
Also, since innumerable false paths need to be automatically detected, a problem arises in that tools utilizing the false path information require increased processing time.